Add routed KiCad PCB file
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README.md
28
README.md
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@ -34,31 +34,9 @@ Open the file in KiCad (create a project if non exists yet). Finalize the PCB in
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1. (Optional) Run the Design Rules Checker. Check the errors. Most of them can be ignored/excluded.
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- All "Footprint not found in libraries" can be ignored completely. This is due to how Ergogen generates the PCB.
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- The "Board edge clearance" violations are mostly about the cutout for the LED chips.
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2. Add VCC and GND planes.
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- Menu: `File -> Board Setup`
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- On "Physical Stackup", change the copper layer number to 4.
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- On "Board Editor Layers", change the type of `In1.Cu` and `In2.Cu` to "power plane".
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- NOTE: `In1.Cu` will be the VCC plane, `In2.Cu` will be a GND plane.
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3. Add filled zones to the VCC and GND planes.
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- Select the `In1.Cu` layer.
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- Use the "Add a filled zone" tool and draw a rectangle that contains the entire board. Assign the zone to VCC.
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- Repeat the same process for the `In2.Cu` layer and assign the zone to GND.
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- The zones don't need to be filled just yet.
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4. Add another filled zone on the `B.Cu` layer and assign it to GND.
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5. Route all signal traces (no VCC or GND yet). Recommended order:
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- Matrix rows (on `B.Cu`)
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- Matrix columns (with vias on `F.Cu`)
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- NeoPixel data pins
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- Connect everything to the MCU.
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6. Route VCC traces.
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- Connect the VCC traces between the NeoPixel chips and the capacitors with a 0.750 mm track.
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- Place free-standing vias (Ctrl+Shift+V) in the middle of the just created VCC traces.
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7. Route GND traces.
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- Draw short GND traces with a 0.750 mm track and a via at the end next to the GND pads of the NeoPixel chips.
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8. Fill all zones by pressing B. Make sure that all nets are routed.
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9. Run the Design Rules Checker and make sure there are no (relevant) violations.
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10. Add some fancy text on the `F.Silkscreen` layer.
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2. Route all signal traces.
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3. Run the Design Rules Checker and make sure there are no (relevant) violations.
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4. Add some fancy text on the `F.Silkscreen` layer.
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#### Export Gerber files
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